(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for the identification of defects or imperfections in components or component elements during the creation of semiconductor devices.
(2) Description of the Prior Art
In the case of faulty operation of semiconductor devices, defects must be located such that the devices under investigation can be compared with nominal or expected behavior of the devices. For this purpose, the method of Voltage Contrast (VC) is applied whereby a voltage of a specific frequency is applied to the point that is being measured, the applied voltage causes secondary electrons to be released by the primary electrons at the point that is being measured. The secondary electrons are observed by a detector and are further amplified into a signal that can be measured and evaluated. Specifically, the observed signal is analyzed for the frequency or frequency spectrum that is emitted by the point under investigation.
Three methods are known in the art for determining whether specific internal periodic signals of a specific frequency are present at the point of observation in a semiconductor circuit. The first method, referred to as voltage coding, images the dynamic voltage of the integrated circuit on a monitor. The second method, referred to as logic state mapping, images the dynamic voltage distribution with the aid of a stroboscope effect. The third method uses locating a specific frequency at the point that is being measured by using a lock-in amplifier. A signal with the sought-for frequency is filtered out-off the response signal after which the intensity of the signal is imaged as a variation in the brightness of the signal.
The passive voltage or voltage coding method is a frequently applied method that can be used to for instance isolate points of leakage in a polysilicon gate. This method however is, as is the case for many of the disciplines that are required for the creation of ever further miniaturized semiconductor devices, also effected by this process of miniaturization. With the increased miniaturization of semiconductor devices, the layer of gate oxide that is created as an interface between the silicon substrate and the overlying gate electrode becomes increasingly thinner. For typical thin layers of gate oxide, a bright voltage contrast is observed due to the tunneling current that is induced in the thin layer of gate oxide. Due to this bright voltage contrast however it is difficult, for thin layers of gate oxide, to identify and distinguish imperfections such as leakage currents in a thin layer of gate oxide. Current practice is to use a constant current to enhance the observable voltage contrast (VC). With the lower thickness of oxide layers, such as layers of gate oxide of about 20 Angstrom thick, this method however is no longer usable and can only be used to distinguish opens and shorts. An alternate method of creating enhanced voltage contrast is provided by the invention.
U.S. Pat. No. 6,091,249 (Talbot et al.) shows an ion-beam and electron-beam in a Voltage Contrast defect detection method.
U.S. Pat. No. 6,201,240 (Dotan et al.) discusses contrast PVC in SEM technology.
U.S. Pat. No. 6,232,787 (Lo et al.) shows the use of VC and electron current in the detection of structure defects.
U.S. Pat. No. 6,038,018 (Yamazaki et al.) and U.S. Pat. No. 4,678,988 (Brust) are related patents.
A principle objective of the invention is to provide an enhanced method of Voltage Contrast (VC) detection for the evaluation of characteristics of deposition of thin layers of semiconductor material.
In accordance with the objectives of the invention a new method is provided for identifying Voltage Contrast that is applied for the evaluation of characteristics of deposition of thin layers of semiconductor material. The voltage contrast is enhanced by applying increased electron beam current, provided by either E-beam or ion-beam current, to the point under investigation.